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ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet Features
* * * * * * * * * * * * Digital compensation of sensor offset, sensitivity, temperature drift and non-linearity Accommodates nearly all bridge sensor types (signal spans from 1 up to 275mV/V processable) Digital one-shot calibration: quick and precise Selectable compensation temperature T1 source: bridge, thermistor, internal diode or external diode Output options: voltage (0...5V), current (4...20mA), PWM, I2C, SPI, ZACwireTM (one-wireinterface), alarm Adjustable output resolution (up to 15 bits) versus sampling rate (up to 3.9kHz) Selectable bridge excitation: ratiometric voltage, constant voltage or constant current Input channel for separate temperature sensor Sensor connection and common mode check (Sensor aging detection) Operation temperature, depending on product version, up to -40..+125C (derated up to +150C) Supply voltage +2.7V...+5.5V Available in SSOP16 or as die
PRELIMINARY Brief Description
ZMD31050 is a CMOS integrated circuit for highlyaccurate amplification and sensor-specific correction of bridge sensor signals. The device provides digital compensation of sensor offset, sensitivity, temperature drift and non-linearity by a 16-bit RISC micro controller running a correction algorithm with correction coefficients stored in non-volatile EEPROM. The ZMD31050 accommodates virtually any bridge sensor (e.g. piezo-resistive, ceramic-thickfilm or steel membrane based). In addition, the IC can interface a separate temperature sensor. The bi-directional digital interfaces (I2C, SPI, ZACwireTM) can be used for a simple PC-controlled one-shot calibration procedure, in order to program a set of calibration coefficients into an on-chip EEPROM. Thus a specific sensor and a ZMD31050 are mated digitally: fast, precise and without the cost overhead associated with laser trimming, or mechanical potentiometer methods. Application kit available (SSOP16 samples, calibration PCB, calibration software, technical documentation) Support for industrial mass calibration available Quick circuit customization possible for large production volumes
Benefits
* * * No external trimming components required PC-controlled configuration and calibration via digital bus interface - simple, low cost High accuracy (0.1% FSO @ -25...85C; 0.25% FSO @ -40...125C)
Application Circuit (Examples)
Fig.1: Ratiometric measurement with voltage output, temperature compensation via external diode
Fig.2: Two wire 4...20mA (5...40V) configuration, temperature compensation via internal diode
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 1/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
Contents
1. CIRCUIT DESCRIPTION ..............................................................................................................3 1.1 SIGNAL FLOW ..............................................................................................................................3 1.2 APPLICATION MODES...................................................................................................................4 1.3 ANALOG FRONT END (AFE) .........................................................................................................5 1.3.1. Programmable Gain Amplifier .............................................................................................5 1.3.2. Analog Sensor Offset Compensation - Analog Zero Point Shift (AZS) ...............................5 1.3.3. Measurement Cycle realized by Multiplexer........................................................................6 1.3.4. Analog-to-Digital Converter .................................................................................................7 1.4 SYSTEM CONTROL.......................................................................................................................8 1.5 OUTPUT STAGE ...........................................................................................................................9 1.5.1. Analog Output ...................................................................................................................10 1.5.2. Comparator Module (ALARM Output) ...............................................................................10 1.5.3. Serial Digital Interface .......................................................................................................10 1.6 VOLTAGE REGULATOR ...............................................................................................................11 1.7 WATCHDOG AND ERROR DETECTION..........................................................................................11 2. 3. 4. 5. 5.1 5.2 5.3 5.4 5.5 6. 6.1 6.2 7. 8. 9. 10. 11. APPLICATION CIRCUIT EXAMPLES........................................................................................12 ESD/LATCH-UP-PROTECTION.................................................................................................13 PIN CONFIGURATION AND PACKAGE ...................................................................................13 IC CHARACTERISTICS .............................................................................................................14 ABSOLUTE MAXIMUM RATINGS...................................................................................................14 OPERATING CONDITIONS (VOLTAGES RELATED TO VSS) ........................................................14 BUILD IN CHARACTERISTICS.......................................................................................................15 ELECTRICAL PARAMETERS (VOLTAGES RELATED TO VSS)......................................................17 INTERFACE CHARACTERISTICS ...................................................................................................18 DIE DIMENSIONS AND PAD COORDINATES..........................................................................19 DIE DIMENSIONS........................................................................................................................19 PAD COORDINATES ...................................................................................................................20 TEST ...........................................................................................................................................20 QUALIFICATION ........................................................................................................................20 PRODUCT VERSIONS / ORDERING CODES...........................................................................21 CUSTOMIZATION ......................................................................................................................21 RELATED DOCUMENTS ...........................................................................................................21
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 2/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
1.
1.1
Circuit Description
Signal Flow
Fig.3: Block diagram of ZMD31050
PGA MUX ADC CMC DAC FIO1 FIO2 PCOMP EEPROM TS ROM PWM programmable gain amplifier multiplexer analog-to-digital converter calibration microcontroller digital-to-analog converter flexible I/O 1: analog out (voltage/current), PWM2, ZACwireTM (one-wire-interface) flexible I/O 2: PWM1, SPI data out, SPI slave select, Alarm1, Alarm2SIF serial interface: I2C data I/O, SPI data in, clock programmable comparator for calibration parameters and configuration on-chip temperature sensor (pn-junction) for correction formula and -algorithm PWM module
The ZMD31050's signal path is partly analog (blue) and partly digital (red). The analog part is realized differential - this means internal is the differential bridge sensor signal also handled via two signal lines, which are rejected symmetrically around a common mode potential (analog ground = VDDA/2). Consequently it is possible to amplify positive and negative input signals, which are located in the common mode range of the signal input. The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The Multiplexer (MUX) transmits the signals from bridge sensor, external diode or separate temperature sensor to the ADC in a certain sequence (instead of the temp. diode the internal pnjunction (TS) can be used optionally). Afterwards the ADC converts these signals into digital values.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 3/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
The digital signal correction takes place in the calibration micro-controller (CMC). It is based on a special correction formula located in the ROM and on sensor-specific coefficients (stored into the EEPROM during calibration). Dependent on the programmed output configuration the corrected sensor signal is output as analog value, as PWM signal or in digital format (SPI, I2C, ZACwireTM ). The output signal is provided at 2 flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can be programmed into the EEPROM via the digital interfaces. The modular circuit concept enables fast custom designs varying these blocks and, as a result, functionality and die size. 1.2 Application Modes
For each application a configuration set has to be established (generally prior to calibration) by programming the on-chip EEPROM regarding to the following modes: - - - - - - -
-
- -
Sensor channel Sensor mode: ratiometric voltage or current supply mode. Input range: The gain of the analog front end has to be chosen with respect to the maximum sensor signal span and to this has also adjusted the zero point of the ADC Additional offset compensation: The extended analog offset compensation has to be enabled if required, e.g. if the sensor offset voltage is near to or larger than the sensor span. Resolution/response time: The A/D converter has to be configured for resolution and converting scheme (first or second order). These settings influence the sampling rate, signal integration time and this way the noise immunity. The Sample Order influences the response time too. Ability to invert the sensor bridge inputs Analog output Choice of output method (voltage value, current loop, PWM) for output register 1. Optional choice of additional output register 2: PWM via IO1 or alarm out module via IO1/2. Digital communication: The preferred protocol and its parameter have to be set. Temperature The temperature measure source for the temperature correction has to be chosen. The temperature measure source T1 sensor type for the temperature correction has to be chosen (only T1 is usable for correction!!!) Optional: the temperature measure channel as the second output has to be chosen. Supply voltage : For non-ratiometric output the voltage regulation has to be configured.
Note: Not all possible combinations of settings are allowed (see section 1.5). The calibration procedure must include - the set of coefficients of calibration calculation and, depending on configuration, - the adjustment of the extended offset compensation, - the zero compensation of temperature measurement, - the adjustment of the bridge current and, if necessary, - the set of thresholds and delays for the alarms and the reference voltage.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 4/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 1.3 Analog Front End (AFE) PRELIMINARY
The analog front end consists of the programmable gain amplifier (PGA), the multiplexer (MUX) and the analog-to-digital converter (ADC). 1.3.1. Programmable Gain Amplifier
The following tables show the adjustable gains, the processable sensor signal spans and the allowed common mode range. PGA Gain Gain Gain Max. span Input range Gain aIN Amp1 Amp2 Amp3 VIN_SP in mV/V VIN_CM in % VDDA 1 420 30 7 2 2 43 - 57 2 280 30 4,66 2 3 38 - 62 3 210 15 7 2 4 43 - 57 4 140 15 4,66 2 6 40 - 59 5 105 15 3,5 2 8 38 - 62 6 70 7,5 4,66 2 12 40 - 59 7 52,5 7,5 3,5 2 16 38 - 62 8 35 3,75 4,66 2 24 40 - 59 9 26,3 3,75 3,5 2 32 38 - 62 10 14 1 7 2 50 43 - 57 11 9,3 1 4,66 2 80 40 - 59 12 7 1 3,5 2 100 38 - 62 13 2,8 1 1,4 2 280 21 - 76 Table 1: Adjustable gains, resulting sensor signal spans and common mode ranges 1.3.2. * * Analog Sensor Offset Compensation - Analog Zero Point Shift (AZS) digital offset correction analog cancellation for large offset values (up to approx 300% of span) No.
The ZMD31050 supports two methods of sensor offset cancellation (zero shift):
Digital sensor offset correction will be processed at the digital signal correction/conditioning by the CMC. Analog sensor offset pre-compensation will be needed for compensation of large offset values, which would be overdrive the analog signal path by uncompensated gaining. For analog sensor offset pre-compensation a compensation voltage will be added in the analog pre-gaining signal path (coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM bits. It allows an Analog Zero Point Shift up to 300% of the processable signal span. The zero point shift of the temperature measurements can also be adjusted by 6 EEPROM bits (ZAZS= -25...+25) and is calculated by: VAZS / VDDBR= k * ZAZS / ( 20 * aIN)
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 5/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet
PGA gain aIN Max. span VIN_SP in mV/V Calculation factor k Offset shift per step in % full span 15% 9% 15% 9% 6% 9% 6% 9% 6% 15% 9% 6% 1%
PRELIMINARY
Approx. maximum Approx. maximum offset shift in mV/V shift in [% VIN_SP] (@ 25) +/- 9 450 +/- 8 266 +/- 18 450 +/- 18 300 +/- 15 187 +/- 33 275 +/- 44 275 +/-66 275 +/- 87 272 +/- 270 540 +/- 250 312 +/- 225 225 +/- 90 32
420 280 210 140 105 70 52,5 35 26,3 14 9,3 7 2,8
2 3 4 6 8 12 16 24 32 50 80 100 280
3,0 1,833 3,0 1,833 1,25 1,833 1,25 1,833 1,25 3,0 1,833 1,25 0,2
Table 2: Analog Zero Point Shift Ranges 1.3.3. Measurement Cycle realized by Multiplexer
The Multiplexer selects, depending on EEPROM settings, the following inputs in a certain sequence. Bridge temperature signal measured by external diode Bridge temperature signal measured by internal pn-junction Bridge temperature signal measured by bridge resistors Separate temperature signal measured by external thermistor Internal offset of the input channel measured by input short circuiting Pre-amplified bridge sensor signal Start routine The complete measurement cycle is controlled by the CMC. The cycle diagram at the right shows its principle structure. The EEPROM adjustable parameters are: Pressure measurement count, n=<1,2,4,8,16,32,64,128> Enable temperature measurement 2, e2=<0,1> After Power ON the start routine is called. It contains the pressure and auto zero measurement. When enabled it measures the temperature and its auto zeros. n 1 n 1 n 1 n * e2 e2 e2 * Pressure measurement Temp 1 auto zero Pressure measurement Temp 1 measurement Pressure measurement Pressure auto zero Pressure measurement Temp 2 auto zero Temp 2 measurement
n * e2 * Pressure measurement
Fig. 4: Measurement cycle ZMD31050
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 6/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 1.3.4. Analog-to-Digital Converter PRELIMINARY
The ADC is a charge balancing converter in full differential switched capacitor technique. It can be used as first or second order converter: In the first order mode it is inherently monotone and insensitive against short and long term instability of the clock frequency. The conversion cycle time depends on the desired resolution and can be roughly calculated by: r tCYC_1 = 2 s The available ADC-resolutions are rADC=<9,10,11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equation: VADC_DIFF /VADC_REF = ZADC / N - RSADC ZOUT: N: VADC_DIFF: VADC_REF: RSADC: number of counts (result of the conversion) r total number of counts (=2 ) differential input voltage of ADC differential reference voltage of ADC digital ADC Range Shift (RSADC = 1/16, 1/8, 1/4, 1/2, controlled by the EEPROM content)
With the RSADC value a sensor input signal can be shifted in the optimal input range of the ADC. In the second order mode two conversions are stacked with the advantage of much shorter conversion cycle time and the drawback of a lower noise immunity caused by the shorter signal integration period. The conversion cycle time at this mode is roughly calculated by: tCYC_2 = 2(r+3)/2 s The available resolutions are rADC=<10,11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equations: VADC_DIFF /VADC_REF = ZADC / N - RSADC ZADC = Z1 * (N2/2) + Z2 N = N1 * 2(INT(r+2)/2) + N2 Z1: Z2: N1: N2 VADC_DIFF: VADC_REF: RSADC: number of counts (result of the 1st conversion) number of counts (result of the 2nd conversion) total number of counts 1st conversion (=2(INT(r+2)/2)) total number of counts 2nd conversion (=2(INT(r+1)/2)) differential input voltage of ADC differential reference voltage of ADC digital ADC Range Shift (RSADC = 1/16, 1/8, 1/4, 1/2, controlled by the EEPROM content)
Note: The AD conversion time is only a part of a whole sample cycle. Thus the sample rate is lower then the AD conversion rate.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 7/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
ADC Order OADC 1
2
Maximum Output Resolution Sample Rate rADC* Digital-OUT Analog-OUT rPWM fCLK=2MHz fCLK =2.25MHz Bit Bit Bit Bit Hz Hz 9 9 9 9 1302 1465 10 10 10 10 781 879 11 11 11 11 434 488 12 12 11 12 230 259 13 13 11 12 115 129 14 14 11 12 59 67 15 15 11 12 30 34 10 10 10 10 3906 4395 11 11 11 11 3906 4395 12 12 11 12 3906 4395 13 13 11 12 1953 2197 14 14 11 12 1953 2197 15 15 11 12 977 1099 Table 2: Output resolution versus sample rate
*ADC Resolution should be 1 or 2 Bits higher then applied Output Resolution 1.4 System Control
The system control has the following features: Control of the I/O relations and of the measurement cycle regarding to the EEPROM-stored configuration data 16 bit correction calculation for each measurement signal using the EEPROM stored calibration coefficients and ROM-based algorithms Started by internal POC, internal clock - generator or external clock For safety improvement the EEPROM data are proved with a signature within initialization procedure, the registers of the CMC are steadily observed with a parity check. Once an error is detected, the error flag of the CMC is set and the outputs are driven to a diagnostic value Note: The conditioning includes up to third order sensor input correction. The available adjustment ranges depend on the specific calibration parameters, a detailed description will be issued later. To give a rough idea: Offset compensation and linear correction are only limited by the loose of resolution it will cause, the second order correction is possible up to about 30% full scale difference to straight line, third order up to about 20% (ADC resolution = 13bit). The temperature calibration includes first and second order correction and should be fairly sufficient in all relevant cases. ADC resolution influences also calibration possibilities - 1 bit more resolution reduces calibration range by approximately 50%.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 8/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 1.5
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
PRELIMINARY
Output Stage
Used serial IF IC X X X X X X X X X X X X X X X X X X X X X X X X X X X Analog Analog Analog PWM2 PWM2 PWM2 Analog Analog Analog Analog Analog Analog PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 ALARM1 PWM1 PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 ALARM2 Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2
2
Used I/O pins OUT IO1 IO2 SDA Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data in Data in Data in Data in Data in Data in Data in Data in Data in -
SPI
The ZMD31050 provides the following I/O pins: OUT, IO1, IO2 and SDA. Via these pins the following signal formats can be output: Analog (voltage/current), PWM, Data (SPI/I2C), Alarm. The following values can be provided at the O/I pins: bridge sensor signal, temperature signal 1, temperature signal 2, alarm. Note: The Alarm signal only refers to the bridge sensor signal, but never to a temperature signal. Due to the necessary pin sharing there are restrictions to the possible combinations of outputs and interface connections. The table beside gives an overview about possible combinations. Note: In the SPI mode the pin IO2 is used as Slave select. Thus no Alarm 2 can be output in this mode.
Table 3: Output configurations overview
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 9/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
1.5.1.
Analog Output
For the analog output 3 registers of 12 bit depth are available, which can store the actual pressure and the results of temperature measurement 1 and 2. Each register can be independently switched to one of two output slots connected to the Pin OUT and IO1 respectively. In these output slots different output modules are available according to the following table: Output slot: OUT Voltage x PWM x Table 5:Analog output configuration IO1 x
The Voltage module consists of an 11bit resistor string - DAC with buffered output and a subsequent inverting amplifier with class AB rail-to-rail OPAMP. The two feedback nets are connected to the Pins FBN and FBP. This structure offers wide flexibility for the output configuration, for example voltage output and 4 to 20 mA current loop output. To short circuit the analog output against VSS or VDDA does not damage the ZMD31050. The PWM module provides pulse streams with signal dependent duty cycle. The PWM - frequency depends on resolution and clock divider. The maximum resolution is 12 bit, the maximum PWM - frequency is 4 kHz (9 bit). If both, second PWM and SPI protocol are activated, the output pin IO1 is shared between the PWM output and the SPI_SDO output of the serial interface (Interface communication interrupts the PWM output). 1.5.2. Comparator Module (ALARM Output)
The comparator module consists of two comparator channels connectable to IO1 and IO2 respectively. Each of them can be independently programmed referring to the parameters threshold, hysteresis, switching direction and on/off - delay, additional a window comparator mode is available. 1.5.3. Serial Digital Interface
The ZMD31050 includes a serial digital interface which is able to communicate in three different communication protocols - I2CTM, SPITM and ZACwireTM (one wire communication). In the SPI mode the pin IO2 operates as slave select input, the pin IO1 as data output. Initializing Communication After power-on the interface is for about 20ms (start window) in the state ZACwire. During the start window it is possible to communicate via the one wire interface (pin OUT). Detecting a proper request inside the start window the interface stays in the state ZACwire. This state can be left by certain commands or a new power-on. If no request happens during the start window then the serial interface switches to I2C or SPI mode (depending on EEPROM settings) and the OUT pin is used as analog output or as PWM output (also depending on EEPROM settings. The start window can generally be disabled (or enabled) by a special EEPROM setting. For detailed description of the serial interfaces see "ZMD31050 Functional Description".
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 10/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 1.6 Voltage Regulator PRELIMINARY
For ratiometric applications 3V to 5V (+/- 10%) the external supply voltage can be used for sensor element biasing. If an absolute analog output is desired then the internal voltage regulator with external power regulation element (FET) can be used. It is bandgap reference based and designed for an external supply range VSUPP = (7 ... 40) VDC. With the voltage regulator the internal supply and sensor bridge voltage can be varied between 3V and 5V. 1.7 Watchdog and Error Detection
The ZMD31050 detects various possible errors. A detected error is signalized by changing in a diagnostic mode. In this case the analog output is set to High or Low (maximum or minimum possible output value) and the output registers of the digital serial interface are set to a significant error code. A watchdog oversees the continuous working of the CMC and the running measurement loop. A check of the sensor bridge for broken wires which is done permanently by two comparators watching the input voltage of each input (between 0.5V ... VDDA-0.5V ). Add on the common mode voltage of the sensor is watched permanently (sensor aging). Different functions and blocks in digital part are watched like RAM-, Rom,- EEPROM- and Register content continuously, the document "ZMD31050 Functional Description" contains in chapter 1.3.4 a detailed description of all watched block and methods of messaging of errors.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 11/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
2.
Application Circuit Examples
ZMD 31050
ZMD 31050
Example 1 Typical ratiometric measurement with voltage output, temperature compensation via external diode, internal VDD regulator and supply lost diagnosis (bridge must not be at VDDA) is used
Example 2 0-10V output configuration, supply regulator, temperature compensation via internal diode, internal VDD regulator and bridge in voltage mode
PWM-Out
ZMD 31050
ZMD 31050
Example 3 Absolute voltage output, constant current biasing of the sensor bridge, temperature compensation by bridge voltage drop measurement, internal VDD regulator without ext. capacitor
Example 4 Ratiometric pressure measurement, 3-wire connection for end of line calibration, additional temperature measurement with external thermistor for PWM-output
Hint: It is possible to combine or split connectivity of different application examples. For VDD generation ZMD recommends to use internal supply voltage regulator with external capacitor (refer to example 1).
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 12/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
3.
ESD/Latch-Up-Protection
All pins have an ESD Protection of >2000V (except the Pins INN,INP,FBP with > 1200V) and a Latchup protection of 100mA or of +8V/ -4V (to VSS/VSSA) - refer chapter 4 for details and restrictions. ESD Protection referred to the human body model is tested with devices in SSOP16 packages during product qualification. The ESD test follows the human body model with 1.5kOhm/100pF based on MIL 883, Method 3015.7.
4.
Pin
10 11 9 1 8 15 6 7 14 16 13 2 12 3 4 5
Pin Configuration and Package
Name
OUT FBP FBN VDDA VDD VSS SCL SDA VINP VINN VBR IN3 IR_TEMP VGATE IO1 IO2
Description
Analog output & PWM2 Output & one wire interface i/o Positive feedback connection output stage Negative feedback connection output stage Positive analog supply voltage Positive digital supply voltage Negative supply voltage IC clock & SPI clock Data IO for IC & data IN for SPI Positive input sensor bridge Negative input sensor bridge Bridge top sensing in bridge current out Resistive temp sensor IN & external clock IN Current source resistor i/o & temp. diode in Gate voltage for external regulator FET SPI data out & ALARM1 & PWM1 Output SPI chip select & ALARM2
Remarks
Analog OUT & dig. IO Analog IO Analog IO Supply Supply Ground
Latch-Up related Application Circuit Restrictions and/or Remarks
free accessibility free accessibility free accessibility only short to VDDA or capacitor to VSS allowed, otherwise no application access
Digital IN, pull-up free accessibility Digital IO, pull-up free accessibility Analog IN Analog IN Analog IO Analog IN Analog IO Analog OUT Digital IO Digital IO free accessibility free accessibility only short to VDDA or connection to sensor bridge, otherwise no application access free accessible (latch-up related) circuitry secures potential inside of VSS-VDDA range, otherwise no application access only connection to external FET free accessibility free accessibility
The standard package of the ZMD31050 is a SSOP16 (5.3mm body width) with lead-pitch 0.65mm:
Pin-Nr 9 10 11 12 13 14 15 16 Pin-Name FBN OUT FBP IR_TEMP VBR VINP VSS VINN Pin-Name VDD SDA SCL IO2 IO1 VGATE IN3 VDDA Pin-Nr 8 7 6 5 4 3 2 1
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 13/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
16
1
ZMD U23456 abcd xxxx YYWW
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
5.
5.1 No. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5
IC Characteristics
Absolute Maximum Ratings Parameter Digital Supply Voltage Analog Supply Voltage Voltage at all analog and digital I/O - Pins Voltage at Pin FBP Storage temperature Symbol VDDAMR VDDAAMR VA_I/O, VD_I/O VFBP_AMR TSTG min -0.3 -0.3 -0.3 -1.2 -45 typ max 6.5 6.5 VDDA +0.3 VDDA +0.3 150 Unit V DC V DC V DC V DC C Conditions to VSS to VSS Exception s. 5.1.4 4 .. 20mA - Interface
5.2 No.
Operating Conditions Parameter Symbol TAMB TAMB_ADV VDDA VDDAADV VDD VSUPP VIN_CM VIN_FBP RBR min -40 -25 2.7 4.5 2.7 VDDA + 2V 0.25 -1 3.0 5.0
2
(Voltages related to VSS) typ max 125 85 5.5 5.5 1.05 40 0.65 VDDA 25.0 25.0 Unit C C V DC ratiometric mode V DC ratiometric mode VDDA external powered V DC V DC voltage regulator mode with ext. JFET VDDA absolute ratings in temperature range1 V DC k k full temperature range 4 .. 20mA - Interface Conditions
5.2.1 Ambient temperature 5.2.2 Ambient temperature advanced performance 5.2.3 Analog Supply Voltage 5.2.4 Analog Supply Voltage advanced performance 5.2.5 Digital Supply Voltage 5.2.6 External Supply Voltage 5.2.7 Common mode input range 5.2.8 Input Voltage Pin FBP 5.2.9 Sensor Bridge Resistance
1 2
See also chapter 1.3.1 no limitations with an external connection between VDDA and VBR
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 14/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
No.
Parameter
Symbol RBR_REF
min 0.07
typ
max
Unit RBR
Conditions ( leads to IBR = VDDA / (16*RRef)) between VDDA and VSS, extern between VDD and VSS, extern Output Voltage mode
5.2.10 Reference Resistor for Bridge Current Source 5.2.11 Stabilization Capacitor 5.2.12 Optional Stabilization Capacitor 5.2.13 Maximum allowed load capacitance at OUT4 5.2.14 Minimum allowed load resistance 5.2.15 Maximum allowed load capacitance at VGATE 5.3 No. Build In Characteristics Parameter
CVDDA CVDD CL_OUT
50 03
100 100
470 470 50
nF nF nF
RL_OUT CL_VGATE
2 10
k nF
Output Voltage mode summarized to all potentials
Symbol VIN_SP
min 1 -20 -25 -31 9
typ
max 275 20 25 31 15
Unit
Conditions
5.3.1. Selectable Input Span, Pressure Measurement 5.3.2 Analog Offset Compensation Range (6 Bit setting) 5.3.3 A/D Resolution 5.3.4 5.3.5 5.3.6 D/A Resolution PWM - Resolution Reference current for external temperature diodes Sensitivity internal temperature diode
mV/V 4 Bit setting s. 3.3.1 count ADJREF:BCUR>3 ADJREF:BCUR=7 3 Bit setting @ analogue output
rADC rDAC rPWM ITS
Bit Bit Bit A
11 9 8 18 12 40
5.3.7
STT_SI
2800 3200
3600
ppm Raw values - without f.s. /K conditioning
3 4
lower stabilization capacitors can increase noise level at the output if used, consider special requirements of ZACwireTM single wire interface stated in "Functional Description" chapter 4.3
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 15/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
5.3.8 Cycle Rate versus A/D-Resolution ( linear related to master clock frequency5 - values calculated at exact 2 MHz ) ADC Order Resolution OADC rADC Bit 1 9 10 11 12 13 14 15 2 11 12 13 14 15 5.3.9 PWM Frequency PWM Resolution rPWM [Bit] 9 10 11 12
5 6
Conversion Cycle fCYC fCLK=2MHz fCLK=2.25MHz Hz Hz 1302 1465 781 879 434 488 230 259 115 129 59 67 30 34 3906 4395 3906 4395 1953 2197 1953 2197 977 1099
PWM Freq./Hz at 2 MHz Clock5 Clock Divider 1 0,5 0,25 0,125 3906 1953 977 488 1953 977 488 244 977 488 244 122 488 244 122 61
PWM Freq./Hz at 2.25 MHz Clock6 Clock Divider 1 0,5 0,25 0,125
4395 2197 1099 549 2197 1099 549 275 1099 549 275 137 549 275 137 69
Internal RC - Oscillator: coarse adjustment to1, 2 and 4 MHz, fine tuning +/- 25% , external clock is also possible Internal RC - Oscillator: coarse adjustment to1.125, 2.25 and 4.5 MHz, fine tuning +/- 25% , external clock is also possible
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 16/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 5.4 No. Electrical Parameters Parameter Symbol min typ max Unit PRELIMINARY (Voltages related to VSS) Conditions
5.4.1.1 Supply current 5.4.1.2 Supply current for current loop 5.4.1.2 Temperature Coeff. Voltage Reference 1 5.4.2.1 Parasitic differential input offset current1 5.4.3.1 Output Signal Range 5.4.3.2 Output Slew rate 1 5.4.3.3 Short circuit current limitation 5.4.4.1 PWM high voltage 5.4.4.2 PWM low voltage 5.4.4.3 PWM output slew rate 5.4.5.1 Sensitivity external diode or resistor meas. 5.4.6.1 Output-High-Level 5.4.6.2 Output-Low-Level 5.4.6.3 Output Current
1
5.4.1 Supply / Regulation ISUPP 2.5 4 ISUPP_CL 2.0 2.5
mA
without bridge current and without load current, fCLK 2.25MHz without bridge current, fCLK 1.2MHz, BiasAdjustment 1
TCREF
-200
+/- 50
200
ppm/K
5.4.2 Analog Front End IIN_OFF -2 -10 2 10 0.975 nA temp. range 5.2.2., TADV
5.4.3 DAC & Analog Output (Pin OUT) VOUT_SR 0.025 SROUT IOUT_max 0.1 5 10 20 VDDA Voltage mode, assuming
maximum load of 2k
V/s mA
Voltage mode, CL<20nF
5.4.4 PWM Output (Pin OUT, IO1) VPWM_H VPWM_L
1
0.9 0.1 15 1450 1520 1590
VDDA VDDA V/s ppm f.s. / mV VDDA 0.1 VDDA mA
RL > 10 k RL > 10 k CL < 1nF Raw values - without conditioning
SRPWM STTS_E
5.4.5 Temperature Sensors (Output IRT)
5.4.6 Digital Outputs (IO1, IO2,OUT in digital mode) VDOUT_H VDOUT_L IDOUT 4 0.9
1
no measurement in serial production, parameter is guarantied by design and/or quality observation
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 17/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 5.4.7 System Response 5.4.7.1 Startup time
12
PRELIMINARY
tSTA
2
5
ms
Power up to first measure result at output, without OWI - start window TADV, VADV (-25...+85C, 4.5...5.5V) ADJREF:BCUR>3 shorted inputs, bandwith 2kHz
5.4.7.2 Response time
tRESP
2/fCON
3/fCON 0.1 0.25 5 500 1000 %
ACOUT 5.4.7.2 Overall accuracy (Deviation from ideal line including INL, gain and offset errors) 5.4.7.3 Peak-to-PeakVOUT_NS Noise@output 5.4.7.4 Ratiometricity Error 5.5 No. Interface Characteristics Parameter Symbol min typ REOUT_5 REOUT_3
mV
ppm 4.5 - 5.0V & 5.0 - 5.5V ppm 2.7 - 3.0V & 3.0 - 3.3V
max
Unit
Conditions
5.5.1 Multiport Serial Interfaces (I2C, SPI) 5.5.1.1 Input-High-Level 5.5.1.2 Input-Low-Level 5.5.1.3 Output-Low-Level 5.5.1.4 load capacitance @ SDA 5.5.1.5 Clock frequency SCL 5.5.2.1 Pullup resistance master 5.5.2.2 OWI line resistance 5.5.2.3 OWI load capacitance 5.5.2.4 Voltage level Low 5.5.2.5 Voltage level High VI2C_IN_H VI2C_IN_L VI2C_OUT_L CSDA fSCL ROWI_PU ROWI_LINE COWI_LOAD VOWI_L VOWI_H 0.75 330 0.05 0.08 0.2 0.7 0 1 0.3 0.1 400 400 VDDA VDDA VDDA pF kHz ROWI_PU tOWI_BIT / ROWI_PU VDDA VDDA
20s < tOWI_BIT < 100s
Open-Drain IOL= -3mA
5.5.2 One Wire Serial Interface (ZACwireTM)
1
no measurement in serial production, parameter is guarantied by design and/or quality observation
Depends on resolution and configuration - start routine begins approximately 0.8ms after power on
2
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 18/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
6.
6.1 * * * * *
Die Dimensions and Pad Coordinates
Die Dimensions Die size (incl. scribeline): 3170m x 2740m 8.7sqmm Core die size (without scribeline): 3020m x 2590m 7.8sqmm Die thickness: 390m Scribeline (distance between two core dice on wafer): 150m Pads size: 68m x 68m (exception: VDDA: 90m x 90m)
96m
146m
Core Die with pads
3020m
y x
ZMD31050
2590m
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 19/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet 6.2 Pad Coordinates PRELIMINARY
All pad coordinates are for pad centers and related to the center of the VDDA pad. Pin-No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VDDA IN3 VGATE IO1 IO2 SCL SDA VDD FBN OUT FBP IR_TEMP VBR VINP VSS VINN X coordinate in m 0 160 650 1320 1560 1800 2050 2740 2370 1890 1580 1340 990 590 320 70 Y coordinate in m 0 0 0 0 0 0 0 0 2400 2400 2400 2400 2400 2400 2400 2400
7.
Test
Functions and parameters given in this datasheet are design objectives and therefore preliminary. The final functions and parameters will be specified later, in a final datasheet. ZMD will assure the final functions and parameters by serial production tests. Depending on the product version (see section 10), different serial production tests will be performed.
8.
Qualification
Depending on the product version (see section 10), different pre-production qualification procedures will be performed. The product versions "automotive" and "extended automotive" (target application area) will be qualified according to AEC-Q100.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 20/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
9.
Product Versions / Ordering Codes
10.
Customization
For high-volume applications, which require an up- or downgraded functionality compared to the ZMD31050, ZMD can customize the circuit design by adding or removing certain functional blocks. For it ZMD has a considerable library of sensor-dedicated circuitry blocks. Thus ZMD can provide a custom solution quickly. Please contact ZMD sales for further information.
11.
* * * * *
Related Documents
ZMD31050 Product Flyer ZMD31050 Feature Sheet ZMD31050 Functional Description ZMD31050 Application Kit Description ZMD31050 Calibration DLL Description
For the current version of this document please look at www.zmd.biz.
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 21/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
ZMD31050
Advanced Differential Sensor Signal Conditioner
Datasheet PRELIMINARY
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. ZMD assumes no obligation regarding future manufacture unless otherwise agreed in writing. The information furnished hereby is believed to be correct and accurate. However, ZMD shall not be liable to any customer, licensee or any other third party for any damages in connection with or arising out of the furnishing, performance or use of this technical data. No obligation or liability to any customer, licensee or any other third party shall result from ZMD's rendering of technical or other services.
For further information:
ZMD AG Grenzstrasse 28 01109 Dresden, Germany Phone +49 (0)351-8822-366 Fax +49 (0)351-8822-337 sales@zmd.de www.zmd.biz
ZMD America, Inc. 201 Old Country Road, Suite 204 Melville, NY 11747, USA Phone +01 (631) 549-2666 Fax +01 (631) 549-2882 sales@zmda.com www.zmd.biz
ZMD America, Inc. 15373 Innovation Drive, Suite 110 San Diego, CA 92128, USA Phone +01 (858) 674-8070 Fax +01 (858) 674-8071 sales@zmda.com www.zmd.biz
Copyright (c) 2005, ZMD AG, Rev. 0.9, 2005-03-02 22/22 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

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